The present invention relates generally to semiconductor devices and their fabrication and, more particularly, to semiconductor devices and their manufacture involving techniques for analyzing and debugging circuitry within an integrated circuit.
The semiconductor industry has recently experienced technological advances that have permitted dramatic increases in circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of hundreds of millions of instructions per second to be packaged in relatively small, air-cooled semiconductor device packages. A by-product of such high-density and high functionality in semiconductor devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the die and on the exterior of the semiconductor packages which receive the die, for connecting the packaged device to external systems, such as a printed circuit board
As the manufacturing processes for semiconductor devices and integrated circuits increase in difficulty, methods for testing and debugging these devices become increasingly important. Not only is it important to ensure that individual chips are functional, it is also important to ensure that batches of chips perform consistently. In addition, the ability to detect a defective manufacturing process early is helpful for reducing the number of defective devices manufactured.
To increase the number of pad sites available for a die, different chip packaging techniques have been used. One technique is referred to as a dual in-line package (DIP) in which bonding pads are along the periphery of the device. Another technique, called controlled-collapse chip connection or flip chip packaging, uses the bonding pads and metal (solder) bumps. The bonding pads need not be on the periphery of the die and hence are moved to the site nearest the transistors and other circuit devices formed in the die. As a result, the electrical path to the pad is shorter. Electrical connections to the package are made when the die is flipped over the package with corresponding bonding pads. Each bump connects to a corresponding package inner lead. The resulting packages have a lower profile and have lower electrical resistance and a shortened electrical path. The output terminals of the package may be ball-shaped conductive-bump contacts (usually solder or other similar conductive material) and are typically disposed in a rectangular array. These packages are occasionally referred to as xe2x80x9cBall Grid Arrayxe2x80x9d (BGA). Alternatively, the output terminals of the package may be pins, and such a package is commonly known as the pin grid array (PGA) package.
For BGA, PGA and other types of packages, once the die is attached to the package, the backside portion of the die remains exposed. The transistors and other circuitry are generally formed in a very thin epitaxially grown silicon layer on a single crystal silicon wafer of which the die is singulated from. In a structural variation, a layer of insulating silicon dioxide is formed on one surface of a single crystal silicon wafer followed by the thin epitaxially grown silicon layer containing the transistors and other circuitry. This wafer structure is termed xe2x80x9csilicon on insulatorxe2x80x9d (SOI) and the silicon dioxide layer is called the xe2x80x9cburied oxide layerxe2x80x9d (BOX). The transistors formed on the SOI structure show decreased drain capacitance, resulting in a faster switch transistor.
The side of the die including the epitaxial layer, containing the transistors and the other active circuitry, is often referred to as the circuit side of the die or front side of the die. The circuit side of the die is positioned very near the package. The circuit side opposes the backside of the die. Between the backside and the circuit side of the die is single crystalline silicon and, in the case of SOI circuits, also a buried oxide layer. The positioning of the circuit side provides many of the advantages of the flip chip.
In some instances the orientation of the die with the circuit side face down on a substrate may be a disadvantage or present new challenges. For example, when a circuit fails or when it is necessary to modify a particular chip, access to the transistors and circuitry near the circuit side is typically obtained only from the backside of the chip. This is challenging for SOI circuits since the transistors are in a very thin layer (about 10 micrometers) of silicon covered by the buried oxide layer (less than about 1 micrometer) and the bulk silicon (greater than 500 micrometers). Thus, the circuit side of the flip chip die is not visible or accessible for viewing using optical or scanning electron microscopy.
Additionally, as designers work to reduce dimensions of circuitry components to increase speed and fit more circuitry on a die, the resulting submicron structure of tightly spaced components presents increased challenges to debugging or modifying the die circuitry. The presence of a buried oxide layer adds to the difficulty. Existing machining and/or milling methods, such as FIB or laser etching, do not provide the needed accuracy and precision required to debug or modify new smaller circuitry components. Damage to surrounding circuitry occurs when attempting to access and modify a particular component using current methods. Thus, any circuit modification requires precise and accurate nanomachining for success.
Initially, modification of a flip chip SOI die requires removal of the majority of the bulk silicon layer from the backside. The die receives two or three steps of thinning in the process. First the die receives global thinning across the whole die surface. Mechanical polishing is one method for global thinning. Local thinning techniques, such as laser microchemical etching, thin the silicon in an area to a level that is thinner than the die size. One method for laser microchemical etching of silicon focuses a laser beam on the backside of the silicon surface to cause local melting of silicon in the presence of chlorine gas. The molten silicon reacts very rapidly with chlorine and forms silicon tetrachloride gas, which leaves the molten (reaction) zone. A specific example silicon-removal process uses the 9850 SiliconEtcher(trademark) tool by Revise, Inc. (Burlington, Mass.). This laser process provides for both local and global thinning by scanning the laser over a part of, or the whole, die surface. The thinning stops short of the buried oxide layer (BOX) of the SOI integrated circuit.
Substrate removal can present difficulties. For instance, removal of too much substrate damages the BOX layer and the circuitry of the die. Further, it is desirable to perform precision operations on suspect circuitry portions without damaging surrounding circuitry. Presently, focused ion beam (FIB) systems are capable of removing substrate, but FIB systems also remove all circuitry components in their path to access suspect circuitry regions. Thus, there is an unmet need for a method and system to perform precision device edits on internal circuitry of flip chip BOX dies without affecting surrounding circuitry of the die.
The present invention is directed to a method and system for nanomachining a semiconductor device having SOI structure using an optical beam. The present invention is exemplified in a number of implementations and applications, some of which are summarized below.
According to an example embodiment, the present invention applies to a thinned backside integrated circuit die having silicon on insulator (SOI) structure. An optical nanomachining system performs device edits to a selected region of the integrated circuit die. The edits can be made, for example, to regions of the circuit buried beneath circuitry or other die structures. In this manner, edits can be made without affecting surrounding circuitry, thereby enhancing semiconductor manufacturing and analysis.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and detailed description which follow more particularly exemplify these embodiments.